On Jitter, the S/PDIF Standard, and Audio DACs.


Norman Tracy


The following is a discussion of how the implementation of the S/PDIF standard used in consumer digital audio (and the closely related professional AES/EBU standard) can effect the fidelity of the recovered analog signal even when all samples are transmitted and recovered correctly.  

1. The point of the exercise is to reconstruct an analog signal, not just move bytes from file to file or onto a display.

2. To reconstruct an analog signal from digital data two things are required, the sampled audio data values AND a clock signal.

 3. In the S/PDIF serial audio data interface used to get data from CD, LD, DAT, DCC, MD, and PC soundcards to external DACs or digital recorders the clock is transmitted along with the audio data as part of the bi-phase mark encoding used. The absolute stability of this clock from the source varies depending on how good the designers were, the parts are, and the adjustments is. Some of the latest research in the area of jitter on this transmitted clock is contained in references #4 and #5 below. These papers show that jitter is a dynamic phenomenon related to both the quality of individual implementations and, counter intuitively, the value of the audio samples being transmitted. Also the wider the bandwidth of the medium used to transmit S/PDIF AES/EBU data the lower the jitter. Reference #5 shows that correct data values are received with bandwidths as low as 400 kHz while jitter levels of the recovered clock improve with wider bandwidths up to 5 MHz.

 4. Popular S/PDIF receiver chips like the Yamaha YM3623B and Crystal CS8412 are NOT crystal controlled but rather recover the necessary clock from internal Phase Locked Loops (PLL) locked onto the incoming data stream. The simple two pin can crystals often seen directly attached to '3623's and '8412's are optional. The 3623 uses the crystal clock to quickly lock onto the S/PDIF signal. The 8412 uses the crystal clock to determine and display the sample rate and jitter level of the S/PDIF signal. Both parts ignore the local crystal clock once locked onto the S/PDIF signal.

 5. Better (i.e. more expensive) outboard DACs use additional tighter PLLs after the receiver chip to further cleanup the clock. Generally there is a trade off between low jitter PLL and wide locking such that low jitter PLLs may result in a DAC being unable or slow to lock onto a high jitter S/PDIF input requiring use of a low jitter Class 1 source as defined in the 'Red Book' spec. from Sony/Philips. This lack of universality and the fact that parts budget spent on low jitter PLLs (like individual crystals for each sample rate) reduces the parts budget for everything else (like filters, DACs, analog circuits, power supplies, and case) leads many designers to leave well enough alone and use the clock straight out of the receiver chip investing the saved resources elsewhere in the design or lowering the cost. This allows the DACs master clock to be strictly a function of the source and interface. A few companies which make both transports and external DACs have implemented schemes in which the S/PDIF signal is supplemented with a second line carrying the master clock back from the external DAC to the transport. In this way the DAC's crystal becomes the master rather than the transport and the problems of recovering a spectrally pure clock are eliminated. No standards for this type of implementation exist. In reference #4 Dr. Hawksford calls for the clock signal to be transmitted on a second S/PDIF line, I know of no actual product which implements this scheme. Sony (in one product) and Arcam send the actual clock, Linn argues this leads to RFI problems and so they send a DC servo voltage which controls a VCOX in the transport.

 6. As stated above accurate reconstruction of the analog waveform requires both correct samples and a accurate clock. A correct sample at the wrong time is just as much an error as an incorrect sample at the right time.

 7. Incorrect samples are rare as the system is quite robust. A few DACs contain digital filters which interpolate across bad samples, most simply mute or allow the data through. Uncorrected bad samples sound like 'clicks' or 'pops'.

 8. A mistimed sample due to clock jitter is a subtle effect usually going unnoticed by casual listeners using low resolution systems. Critical listeners report a variety of sonic effects related to the subtle details of reproduced sound including but not limited to high frequency details, the nature of reverberation, ambient sounds, and 'grain'. Information theory characterizes jitter as noise accompanying the clock signal. The variety of sonic effects reported by listeners may be accounted for by the fact that the jitter noise spectrum effects how its error is superimposed on the desired signal. Jitter with a white noise spectrum results in the systems noise floor being raised. When jitter noise has specific frequencies present these frequencies tend to show up as side bands on the desired output. See reference #1. In reference #2 Dr. Hawksford reports that a 1 LSB error of a 15kHz signal results from only 0.324 nS of clock error. In reference #2 Steven Harris states "For example, 2 nS peak white noise clock jitter will degrade a perfect 16-bit ADC from a dynamic range of 98 db to 91 db. To reduce clock jitter effects to less than 0.5 db impact on dynamic range, the peak jitter amplitude has to be less than 400 ps." The Harris paper is on jitter effects on ADCs using both measurements of actual devices and computer simulations. I believe the results apply to DACs as well.

9. The threshold of audibility of these effects is a matter of considerable controversy. Seventy years after the introduction of electrical amplification of musical signals a consensus has yet to be reached throughout the audio community as to the threshold of distortion in its many forms. I fear it will take that long again for consensus to develop regarding the distortion mechanisms unique to digital audio. Compounding the difficulty is the fact that a set of instruments to measure jitter at the levels of interest and analyze its effects has an entry price tag into five figures in US $.

10. Then comes a certain group of audiophiles who declare digital audio by its very nature is already perfect. They argue this point using a selected subset of the facts and tenuous analogy to other usually purely digital technologies. Their belief system includes a form of audio egalitarianism which has latched onto digital audio as a means to bring ultimate hi-fidelity down to the lowest common denominator. Anyone questioning this belief system is to be labeled self-delusional or a charlatan and immediately challenged to a duel in the form of an ABX test.


#1 The Jitter Game, Robert Harley; Stereophile January 1993

#2 A Digital Discourse, Dr. Malcolm Hawksford; HiFi News & Record Review Feb,April, June, Aug, 1990

#3 The Effects of Sampling Clock Jitter on Nyquist Sampling ADCs, and on Oversampling Delta Sigma ADCs, Steven Harris; Journal Audio Engineering Society, July 1990

#4 Is the AES/EBU-S/PDIF Digital Audio Interface Flawed?, Chris Dunn & Dr. Malcolm Hawksford; Audio Engineering Society preprint

#5 Jitter: Specification and Assessment in Digital Audio Equipment, Julian Dunn; Audio Engineering Society preprint

Preprints are available for $5 ea. from:

Audio Engineering Society

60 East 42nd Street

NY NY 10165 USA