XD0

 

 

For many years the hi-fi DAC kits X-DAC 3.0 and X-DAC 3.0 Signature were the premier product offering from Audio Crafters Guild. As more advanced formats and parts became available the X-DAC 3.24 R&D platform convincingly demonstrated the sonic thrills and musical satisfaction available from these advances. All this performance was to be offered in the Audio Crafters Guild DAC kit XD0. Alas, before the XD0 could be completed a computer crash took out the engineering CAD files and before these could be recreated the chips sets became obsolete. The following design story remains posted for those interested in the technology of audio hi-fi DACs. It is my intent that in 2008 an updated version of the XD0 will be created using the latest technology.

Norman Tracy

 

XD0 - Introduction

XD0 is a 24 bit 44k-192k PCM/DSD high fidelity digital to analog converter. Based on the dual mode PCM or DSD format Crystal Semiconductor CS43122 DAC chip XD0 implements it in such a way that configurations from the simple to complex can be accommodated. Partnering with the CS43122 DAC is Crystal's CS8420 DIR/SRC digital input receiver, output transmitter, and sample rate converter. The CS8420 is critical to the design because it enables both high performance today and flexibility for tomorrow. Right now CS8420 allows input formats S/PDIF (Sony Philips Digital InterFace) and I2S (I squared S) along with asynchronous jitter reduction and up-sampling to 96k. The I2S I/O and multiple synchronous and asynchronous configurations of CS8420 should allow accommodation of future digital audio data transmission formats.

Ten on board voltage regulators feed the DIR, DAC, clock, and analog stages. These include a high-speed regulator for the DAC and dual shunt regulators in series to scrub noise off the master oscillator's power to lower jitter. The external power source options include simple wall warts, single or multiple ACG SSPS, and for the truly esoteric battery power.

Analog stages for XD0 come in flavors to fit all tastes. On board the INA103 differential-amp gives outstanding results. For those with a passion for tubes an off-board differential follower fed from a tube shunt regulator does the trick with the elegant simplicity of a single stage DAC->tube solution. Finally at the edge of the art successful experiments using that old standby the nickel core audio transformer are already offering sound with amazing musical texture and grace.

The circuit will be implemented on a four layer PCB. Passive parts quality is outstanding including WIMA polypropylene caps, Black-Gate (or Os-Con) electrolytic caps surround the DAC and analog stages, and most other parts are SMD for the lowest possible lead inductance effects. The PCB layout is maniacally tight as the concept of shortest possible lead and trace lengths is taken to the extreme. Parts are mounted on both sides of the board allowing critical circuit elements to literally sit on top of each other. Controlled RF impedance nodes on the power supply lines define circuit subsystems current paths into tight localized loops minimizing cross talk and RFI effects.

Before going further into the details of XD0 lets explore how the concept and design of XD0 came to be.

The genesis of XD0

Some of you are reading this with skepticism having heard my promises for a project called XD5. Through 2000 and 2001 I worked on this design and the X-DAC 3.24 upgrade for ACG's X-DAC 3.0. In hindsight, the biggest lie I told during that period was that XD5 would be ready in "just a few weeks". In April of 2001 I wrote of XD5:

"The status of XD5 is the design is very nearly complete. Schematics run to eight pages thus far. The initial version will be similar to X-DAC 3.24 in that it will use the CS8420 and CS4396/4397/43122 chip set. Thanks to the modular nature of XD5 this can later be configured to work with other DACs that prove worthy such as the PCM1704. But again if this is to see the light of day I must guard against feature creep. It is a delicate balancing act keeping the design open enough to fulfill its mandate to be modular and updateable while limiting it to a point where we can "shoot the design engineer" and get on with a physical realization in the real world."

Despite having successfully identified feature creep as project enemy #1 I ultimately failed to get XD5 off it's schematic and into the real world. In hindsight I can see that the highly modular nature of XD5 was too heavy a burden for the project to carry. The XD5 is modular with a motherboard mainly tasked with heroic levels of power supply and signal distribution between modules. Modules planned included DIR, SRC/AJR, DAC, ADC, master clock with multiple selectable sample rates, and analog stages. The design grew like Topsy as multiple solutions for sub-systems like analog stage, clock, SRC, and of course every new DAC that came along. Issues from these rippled through the XD5 design process like waves on a pond. The siren song of beckoning technology kept the design's subsystems in a constant state of flux. With that flux preventing the details from being nailed down the circuit boards layout never progressed beyond preliminary studies. In a commercial setting with a team of engineers and technicians to bring to bear XD5 would be a relatively simple project to push to completion. As a one-man show with the design only serviced with time borrowed from career and family the project's to-do list eventually overwhelmed this designer.

Outside in the real world hi-fi digital audio was being rocked by the introduction of SACD and DVD-A. Audio journalists declared a format war and their incessant harping on "who will win" and doomsday scenarios of orphaned software sounded the death knell for many products in the separate high end DAC market. Thus the prospects for XD5 being much of a commercial success, or even earning back its development costs, faded more with the arrival of every new issue of Stereophile. Content providers seized on the new formats as an excuse to try and stuff the Napster genie back into her bottle. This resulted in the data stream of the new formats being protected by layers of encryption, license fees, the rule of law, and closed standards. Not a wonderful time to be bringing XD5 to market.

Progress with ACG's R&D program did happen even during those uncertain days. The 24 bit 96k Hz upgrade for X-DAC 3.0 the X-DAC 3.24 came on-line. The sonics of that combination of John Camelle's JC811 regulator, the Crystal CS8420/43122 chipset, Black Gate caps, and low jitter master clock is a revelation. While struggling to tame the XD5 design I was listening to my favorite CDs reveal a wealth of new musical detail and emotional impact through X-DAC 3.24. One day the concept of returning to first principals arose. It was time to set aside attempts at the be-all, do-all DAC in favor of a simpler design. Why not bring the X-DAC 3.24 circuit out as a stand-alone design not dependent on having a base X-DAC 3.0 to build on? The spark that ignited XD0 came was the concept of doing a DAC in the same form factor as the CD/DVD/SACD disk. This brought it all together. The now proven X-DAC 3.24 circuit would fit on a 5" disk and the spiraling complexity of XD5 would be avoided by the physical constraints of keeping only those circuit elements which will fit on a 5" circle.

Saul Marantz revealed in an interview how when he designed the classic Marantz products like the Model 7 preamp he would start with a layout of the front panel and let the design form back from there. When I first read that the audio dweeb in me, who worships at the alter of performance first everything else be damned, though he had it backwards. First the circuit and its demands must be formed and the rest of the device then tailored from the inside out. XD5 and XD0 taught me the wisdom of the master audio artisan Saul Marantz's method. Something must define a design's limits else it will be ever in a state of flux and never reach fruition. The challenge is to define the limit broadly enough that a very high level of performance can be obtained while setting boundaries which allow a project to be brought to closure in a timely manner. X-DAC 3.24 validated the concept that led to XD0 as one delivering very high performance within boundaries that balanced adequate resources vs. extravagance.

I chose to reset the model number for this project back to zero because it represents important aspects of the design. The first is a return to a concept of simplicity and high performance over features. That is borrowing Albert Einstein's concept that we strive to make it "as simple as possible, yet no simpler". Next is that the number zero is a circle like the chosen shape for XD0's printed circuit board. There is something at a gut level about a circle that appeals. Our civilization's technology is based on wheels and from ox carts to satellite antennas, the form serves us well. Finally as a product XD0 represents a new beginning for Audio Crafters Guild. Based on counting the digital audio designs I have authored since I began tweaking CD players in 1988 the model number should be 24 or 54 or maybe even 94! Instead, it seems only fitting that this design be called XD0. X for 'experimental' like the X-1 and X-15 rocket planes I so admired as a boy. D for 'digital to analog converter' is denoting XD0's function. And 0 signaling a concept striving to be our best work yet by returning to first principles of high-end audio design.

XD0 Theory Of Operation

The following theory of operation assumes you have downloaded the schematics (here is the schematic download page). Thus we will start with the first page and take each in turn. A complete understanding of the XD0 circuit requires study of the manufacturer's data sheets for the major integrated circuits used. Sources for these include:

www.crystal.com (CS8420 & CS4312)

www.ti.com (INA103)

www.analog.com (AD811)

XD0 DIR, AJR Filter, Upsampler

This part of the circuit is dedicated to the care and feeding of the Crystal Semiconductor CS8420 Digital Audio Sample Rate Converter. The CS8420 is instrumental in achieving the twin goals of state of the art sound today along with compatibility with the formats of tomorrow. This can be accomplished because the CS8420 combines multiple data input and output options with an advanced sample rate converter. Two examples of the many configurations possible will illustrate:

1. S/PDIF input I2S output with Upsampling and Asynchronous Jitter Reduction

Stereo 16 bit 44.1kHz data is input to the CS8420 via the S/PDIF port. Once the audio data is recovered it is upsampled to 24 bit 96kHz using XD0's local low jitter oscillator and the CS8420 DSP block. Thus formatted to take full advantage of the following DAC the music data is output in I2S format.

2. I2S input and output with or without signal processing.

In the future should the need arise to use XD0 with USB, IEEE1394 (a.k.a. 'Firewire' or 'iLink'), or a yet to be invented format the CS8420 can be configured to accept data on its I2S input and pass it directly onto I2S output. Upsampling and Asynchronous Jitter Reduction DSP functions can be engaged or bypassed as the future format demands and experience shows sounds best.

Refer to the XD0 schematic sheet 1 titled "XD0 DIR, AJR Filter, Upsampler" for the following discussion of circuit details. Starting in the upper left-hand corner grid A1 a set of pull-up or pull-down jumpers are connected to eight pins of U1 CS8420. These are multipurpose pins in that at power up and when coming out of reset (i.e. pin 9 low to high) the CS8420 senses if these are pulled up or down and configures itself accordingly. Note the 47k ohm resistors used which allow the pins to then be used as input and outputs. For example pin 18 SDOUT is used both at power up to help configure the CS8420 and then as an output for serial data. This scheme is only used with the CS8420 in hardware mode, note the pull up resistor on pin 24 placing the chip in HW mode. The CS8420 can also be configured using a microcontroller. This can be implemented in the future using the CONFIG0-2 header connected to U1 pins 2, 20, and 27 to interface U1 to a microcontroller.

On the left side of U1 (grid B3) on U1 pins 4, 5, 12, 13, and 14 are data input to the device. Connections are detailed on XD0 schematic sheet 2. Note that pins 4 and 5 are the industry standard S/PDIF (a.k.a. AES3) data input. Pins 12, 13, and 14 are the serial in I2S (I squared S) inputs. Note that in some CS8420 modes, which do not use these serial inputs, pin 14 becomes a MUTE input.

Along the top of U1 (grid B2) we first encounter pins 10 (RMCK = Recovered Master ClocK) and 11 (RERR = Read ERRor). In synchronous modes when the clock recovered off the S/PDIF data stream by the CS8420's PLL is used it is output on pin 10 RMCK. It is not intended for this to be a typical mode for XD0 however is brought out to a header for those who wish to experiment with synchronous modes. RERR signals that the CS8420 is unable to read or lock onto its incoming data stream. It is sent to the DAC to mute it in the presence of corrupt or zero data.

Next on U1 is pin 8 FILT. This connects the external RC network which completes the CS8420 PLL (Phase Locked Loop) used in recovering the clock from S/PDIF data streams. The RC time constants established by CRIP, CFILT, and RFILT are critical. The values shown are proven using X-DAC 3.24 to provide reliable operation. While experimentation and tweaking are always encouraged be aware there are RC values, including published values, that will prevent the CS8420 from ever locking onto incoming data streams.

The final four pins drawn along the top of U1 are the power and ground pairs for the device's analog (pins 6 & 7) and digital (pins 22 & 23) sections. In keeping with the designs proven in X-DAC 3.0 and X-DAC 3.24 these are powered off separate regulators. Analog power (VEE) feeds a LM2950 5-volt regulator/reference and associated filter components to power U1's VA+ pin. Along the way final filtering chores are accomplished using a pair of low impedance electrolytic caps and a 0.1 SMD cap right at the analog power and ground pins. Digital power into VD+ receives similar filtering after being sourced from U8 a more typical 3-pin regulator. Note the resistor R2 loading the regulator forcing it into a more linear operation region and aiding testing before U1 is installed. Also note that U8 feeds other XD0 circuit elements requiring 'digital' power (NOT including the DAC, see below).

The 'control' pins for U1 CS8420 are drawn along the bottom of the device schematic grids B3 and C3 on the XD0 sheet 1 schematic. Detailed descriptions of all the CS8420 control functions is beyond the scope of this document. Refer to the CS8420 manufacture's data sheet. Two points are worth noting here. The emphasis flag is output on pin 3 U/EMPH. Pin 19 V/AUDIO is intended to flag if the AES3 In data the CS8420 is receiving is 'audio' (CD/DVD format stereo) or 'video' (dolby digital or DTS soundtrack). This signal is OR'ed with the RERR signal using U5 Or-gate. The intent is to mute the DAC using the output of U5 on bad data OR DD/DTS data (which the CS43122 cannot convert). Note the dotted line connecting U5 pins 2 and 4. That is there because as of this writing the V/AUDIO signal from CS8420 does not work in hardware mode. Until this bug is fixed U5 can be left off and the RERR signal jumpered across as shown.

The final function aspects of U1 are the CS8420 outputs drawn along the right side of its schematic symbol grids C2 and C3. Pins 25 and 26 are the CS8420 S/PDIF (AES3) output. While not typically used with XD0 connections are provided allowing use of XD0 for such functions as a S/PDIF 'jitter buster' filter or upsampler. Output Master ClocK (OMCK) is on U1 pin 21. This is an input, the 'output' in its name refers to the fact it is the clock used by the CS8420 sample rate converter to compute an output sample rate. The XD0 low jitter master clock is input to this pin enabling asynchronous jitter reduction and upsampling. Serial output of the audio data uses three pins to carry the data, a word clock, and a bit clock. Pin 17 OLRCK is the Output Left Right ClocK which functions to both denote the beginning of each 16-24 bit sample and also label it as being part of the left or right channel signal. Pin 16 OSCLK the Output Serial data ClocK is the 'bit' clock which defines the individual bits making up the audio samples. Pin 18 SDOUT is the Serial Data OUTput on which the audio data samples are output as alternate Left/Right samples. Note that in some CS8420 modes OLRCK and OSCLK can be inputs, they are referred to as outputs above because this is how they are used on XD0.

XD0 Digital I/O Connections

Refer to the XD0 schematic sheet 2 titled "XD0 Digital I/O Connections". The function of this circuitry is to get data into and out of the CS8420 then pass it onto the CS43122 DAC. The goal is to accomplish these tasks with both high performance and maximum flexibility. The trick being to accommodate the flexibility without compromising fidelity.

In the upper left-hand corner of sheet 2 is connector I2SIN used to input 'I squared S' format data, output recovered master clock, and set MUTE. In typical XD0 configurations which input digital audio data via S/PDIF and use Asynchronous Jitter Reduction only the MUTE jumper (pin 5-6) on I2SIN is used to set U1 pin 14 high or low. In a synchronously configured XD0 (i.e. S/PDIF recovered master clock used instead of local oscillator) the master clock at 256x Fs is available on I2SIN pin 1. Finally should I2S inputs be used instead of S/PDIF these are input on I2SIN pins 2, 3, & 4.

The upper right-hand corner of sheet 2 contains S/PDIF input and output comprised of connectors J1 & J2 and transformers X1 & X2 along with their associated impedance matching resistors and blocking capacitors. For a typical XD0 configuration functioning as an S/PDIF input hi-fi DAC the S/PDIF output circuit around J2 & X2 is not installed. The unlabeled capacitors to the left of J1 & J2 are there to remind us it is a good idea to provide RF bypass to chassis ground when the signal enters the chassis. As such they are of course not included on the XD0 PCB. Jack J1 and transformer X1 are used in the typical XD0 configuration as the S/PDIF input. To maximize performance J1 is an impedance matched precision miniature SMB connector. The intent is this is used to connect the XD0 PCB (printed circuit board) to the RCA or (preferably) BNC connector on the case back panel. Transformers X1 and X2 are very wide-band high noise rejection SMD types designed to accept to 96k sample rates.

The bottom half of sheet 2 is dedicated to getting data and clocks from DIR/SRC U1 to the DAC U2. The 2x10 header J5/6 Expansion Port normally jumpers data from U1 to U2. When the time comes to update or expand XD0's capabilities the Expansion Port allows access to the relevant signals. Note that the pin 1 pairs on J5/6 are VDD power and ground. Thus future modules will be designed to plug into Expansion Port which can provide signal I/O, power, and ground. The clock and data signals which transverse Expansion Port are laid out with inputs right across from outputs. Thus when Expansion Port is not needed simple 0.1" wire jumpers can be soldered in place of the connector. When a connector is used in the Expansion Port each signal pin is placed between a ground pin for maximum signal integrity.

Audio data is carried on Expansion Port pins 9. For easy reference the three clocks are labeled with their frequency as a multiple of Fs the sample rate. The word clock, also called left right clock, is Fs and resides on pins 5. The sample clock runs at 64 x Fs across pins 7. Finally, and most critically, is master clock at a frequency of 256 x Fs on pins 3. When XD0 is operating in asynchronous mode the master clock originates from local low jitter oscillators OSC1 or OSC2 (see sheet 7) joining the bus between R13 and J5 pin 3. From there it goes to both the DIR/SRC and DAC. R13 is an example of the 75-ohm resistors placed in all the high speed digital signal lines. Acting with the input capacitance of the IC into which the signal leads the resulting RC network filters off the highest radio frequencies of the signal. This slight rounding of the pulses' leading edge does not effect the clock or data integrity. It does reduce RFI (radio frequency interference) and the resulting tendency of these signals to get into places they should not.

XD0 CS4396/7/122 DAC Stage

Refer to the XD0 schematic sheet 3 titled "XD0 CS4396/7/122 DAC Stage". Here we come to the heart of XD0 the digital to analog converter (DAC). As the rather peculiar name implies this circuit accommodates any of Crystal Semiconductor's pin compatible high performance DAC chips the CS4396, CS4397, or CS43122. Of course among these the latest CS43122 with its 122 dB dynamic range and dual PCM/DSD compatibility is preferred. Should the CS43122 not be available development with X-DAC 3.24 proved the CS4396 and CS4397 are also fantastic sounding choices. Whichever DAC is loaded on the PCB the surrounding circuitry documented on XD0 schematic sheet 3 has been developed to allow it to perform beyond the level found in typical commercial products.

The power supply of any DAC that aspires to performance beyond 16 bits is critical. Its impossible to make the regulators feeding a 24 bit DAC too good. Here is a DAC offering 122 dB dynamic range yet it only has 60 dB of PSRR (power supply rejection ratio)! The short version is you ARE going to hear what is going on with that regulator. Something with performance far beyond the ordinary is called for. That something is the JC811 regulator.

JC811 Regulator

The JC811 regulator is named in honor of my late and sorely missed electrical engineering and audio design mentor John Cammille. John had a passion for low noise very wide bandwidth circuits. He taught me that for a regulator to have a chance at state of the art performance it must have a wider bandwidth than the circuit it supplies. This is rarely achieved in typical commercial designs because wide bandwidth regulators are prone to oscillation unless very carefully designed and implemented. And an oscillating regulator is just a noise source that is rather contrary to the other desired characteristic of regulators to supply a stable low noise voltage. In one of his brilliant pieces of lateral thinking John Cammille noticed the new transimpedance video op-amps like Analog Devices' AD811 are tailor made to act as wide bandwidth low noise regulators. A look at some of the AD811 specifications reveals just why it such a great device for this application:

140 MHz Bandwidth (3 dB, G = +1)

2500 V/ms Slew Rate

70 dB Power Supply Rejection Ratio

100 mA Output Current

1.9 nV/rootHz Input Voltage Noise

On XD0 schematic sheet 3 titled "XD0 CS4396/7/122 DAC Stage" the JC811 regulator feeding the DAC is located on grids C1 and D1 upper right hand corner of the page. John's original design featured his signature massive filtering of all voltages looking to wipe out that last nV of noise. X-DAC 3.24 demonstrated the simplified design presented here delivered the goods while offering a more compact PCB layout and lower hit on the parts budget. Analog power VEE feeds U6 the AD811 and voltage reference U7 a LM2950. Input voltage to U7 is filtered by L2 & C19. The 5 volt output is further filtered by R14 and C18. This 5 volt reference is used twice on XD0. Via R14 to reference the JC811 regulator and through FB3 to the VREF input of the CS43122 DAC chip. U6 is configured as a transimpedance op-amp circuit with the 5 volt reference input on plus input pin 3. Feedback through R80 goes to negative input pin 2 forcing output pin 6 to track the 5 volts on pin 3. Note that owing to the characteristics of transimpedance op-amps the circuit gain is not exactly 1.0x so output voltage runs about 5.1 volts.

Circuit layout of such a wide bandwidth feedback design is critical. Taking advantage of both through hole and surface mount parts the entire JC811 regulator occupies less than one square inch of PCB real estate! For example note how by using the 8-pin DIP version of AD811 mounted on the bottom of the PCB the SMD feedback resistor R80 can be mounted directly between pins 2 and 6 for a trace length of only 0.25".

CS43122 I/O and Control

Once the quiet hyper-fast regulated voltage leaves the JC811 regulator it powers U2 the CS43122 DAC with additional de-coupling via C13-C16. The combination of Black Gate 10uF and SMD 0.1 uF caps right off the power and ground pins used here proved on X-DAC 3.24 to offer outstanding results. FB2 is included to isolate the analog and digital sides. In the past it was common practice to power the analog and digital sides of DAC chips from separate regulators. Leaving off FB2 provides access to try that on XD0. Experience with X-DAC 3.24 confirmed advice from many application engineers at the IC manufacturers to use common supplies and grounds. The old practice of using split supplies and split ground planes under DAC chips leads to voltage differentials inside the chip. Voltage differentials lead to current flow, in this case between digital and analog sides of the chip. This leads to noise currents and voltages inside the DAC chip we are tasking with resolving -122 dB below 2 volts! Worse case for a DAC powered from separate 'analog' and 'digital' regulators is when one of them fails or is slow to come on. Then the chip sees a full 5 volts differential across its die. Most survive this abuse but I always wondered if the last couple of bits of performance had been degraded. Thus I opt for the performance, safety, and simplicity of sharing a single very good regulator.

After power the second most critical nodes of the CS43122 are CMOUT on pin 25 and FILT+ FILT- on pins 26 & 27. These are used to connect external capacitors to filter the reference voltage the DAC will use to reconstruct the analog waveform. Other DAC chips choose to eliminate these in favor of completely internal integrated references. I REALLY like the fact the designers of CS43122 gave us the flexibility and performance enhancements afforded by keeping the external connections. Experience all the way back to the 18 bit CS4328 shows the cap(s) on this node are very audible and effect the final 'voicing' of the completed design. The X-DAC 3.24 R&D program proved the combination of dual Black Gate 10uF and SMD 0.1 uF caps right off the device pins again sounds fantastic at this node. The form factor of these parts was chosen to allow future experimentation with other low impedance caps such as Sanyo Os-Cons and Panasonic FA series.

The differential analog audio outputs appear on AOUTL- (pin 24), AOUTL+ (pin 23), AOUTR- (pin 19), and AOUTR+ (pin 20). Specifics of the output's characteristics can be found in the CS43122 data sheet.

The clocks and audio data are input on pins 10-13. Note more RFI reduction resistors on these lines R15-R18.

Configuration of the CS43122 in hardware mode (note pin 16 C/H is grounded) is set using RP5 and JP13-17 feeding M0-M4. JP13-17 could also be used in the future to connect a microcontroller to control CS43122 in software mode (after lifting pin 16). JP12 and the connection to M3 of the EMPH signal allows a limited implementation of de-emphasis. As shown by the table in the upper left-hand corner of the schematic this only works at the 44k sample rate. Thus a trade-off exists for full implementation of the CD specification vs. the sonic benefits of upsampling to 96k/24 bits.

Finally, reset and mute inputs are brought into U2 on pins 1 and 15 respectively. A mute control output from pin 17 is not used by XD0, a connection to it is provided should it be needed in the future.

XD0 Analog Stage

Refer to the XD0 schematic sheet 4 titled "XD0 Analog Stage". XD0's analog stage was proven on X-DAC 3.24. In my audio gear-head fantasies the analog stage would be much more complex and exotic than the INA103 based design ultimately selected for XD0. This simple design was brought over from X-DAC 3.24 because it sounds so amazingly fine. When X-DAC 3.24 was designed space constraints of fitting the daughter boards used for the upgrade on and among the existing X-DAC 3.0 parts forced the use of a simple design and smaller than usual power rail caps. Also there was no room for exotic power supply regulators so power had to be tapped off X-DAC 3.0 analog stage regulators. Number and size of parts was limited so only the finest were used. The Burr-Brown (now TI) INA103 differential amp was designed specifically as a high-fidelity audio part featuring both low noise and high output drive capability. Surrounding it are caps from WIMA and Black Gate. Thus configured the INA103 really sings.

The left and right channels are identical, this discussion refers to the left channel components. Positive and inverted inputs enter U9 on pins 1 and 16. Per the manufacturer's recommendation, ferrite beads FB4 and FB6 are available to block RFI from the amp. Resistor RG1 connecting pins 13 and 15 to 2 and 6 sets the amp's gain. Leaving it open (i.e. not installed) sets gain to 1x the XD0 default. Power for the amp enters on pins 8 and 9 after being filtered by the polypropylene and low-Z electrolytic caps discussed above. The INA103 is a differential amp so the difference between pins 1 and 16 appears on output pin 10. This accomplishing both differential to single-ended conversion and the removal of the 2.5v DC offsets present on the raw DAC outputs. Thanks to the precision of the INA103 it can be DC coupled to the outside world using only buffer resistor R24 to guard against high capacitance loads. U9's SENSE and REF pins are star connected back from the output pads completing the standard output stage. The optional vacuum tube analog stage will be discussed below.

XD0 Power Regulators

Regulators for the core devices CS8420 and CS43122 have already been discussed as they are drawn on the sheets of their respective devices. Where possible I do this reflecting my belief that the power and ground system is an integral and vital part of any high performance audio device. Too often these are tacked on as after thoughts this reflected by drawing them on the last page of the schematic package. The regulators on the next two pages are just as vital to their respective subsystems but would not fit on the pages with the circuits they service.

The master clock oscillators selected for XD0 are very low jitter devices. However, like any clock circuit in circuit performance is governed by actual physical implementation. A big part of this is how clean the power being fed to the clock is. The XD0 Clock Twin Shunt Regulator is an all out assault on getting the clock power as low noise as possible to absolutely minimize jitter.

Refer to the XD0 schematic sheet 5 titled "XD0 Clock Twin Shunt Regulator"

When I found this circuit on a oscillator manufacturer's web site it was one of those slap yourself and exclaim "why didn't I think of that!" moments. Series regulators are the workhorses of all electronics. Efficient, easy, and cheap we find them everywhere in everything. While excelling at the DC parameters of importance to most circuits typical series regulators are not as quiet or regulate at as high a frequency as would be ideal for precision analog work. This is a trade-off between being easy to use (low bandwidth = easy to implement) vs. absolute performance. Thus more audio band and RF band noise get through the common 3-terminal regulator than we want on a high precision clock supply. In contrast, shunt regulators are rare, inefficient, and a bit exotic. The inefficiency stems from the fact they need a resistor in series with the power buss against which a transistor or tube works shunting excess voltage and noise to ground. Because of this, resistor shunt regulators waste a lot of energy as heat if asked to drop many volts between source and load. However thanks to the direct path to ground shunt regulators excel at wide band noise reduction. What we see in this circuit is a clever hybrid using both types playing to the advantages of each. A series regulator does the heavy lifting of gross voltage regulation followed by dual shunt regulators assigned the task of scrubbing off AC noise from the DC voltage.

Referring to XD0 schematic sheet 5 titled "XD0 Clock Twin Shunt Regulator" in grid A1 one sees a typical 3-terminal series regulator U11 and its associated circuitry. The only tricks here are generous sized filter caps, long time constants on the v-set Rs and a load resistor to aid testing and bias it up. This delivers about as good a performance as one gets from the 3-terminal integrated regulator. The series regulator takes VEE analog voltage in to 5 volts DC out.

Onto the center B and C columns of the schematic one finds the dual series connected shunt regulators. Shunt resistors R26 and R36 interrupt the power buss giving shunt transistors U12 and U15 a current limit to work against. Note the very low value of R26/36. Without the pre-regulation of U11 these would have to be much larger as would the current rating of U12 & U15. Because they only work on mV and uV of AC noise the small values and dissipation here are fine. Dual op-amp U13 forms the error amps. They sample the voltage and generate drive to U12 and U15. One of these shunt regulators so configured gives 30-40 dB of noise reduction. With two in series noise should be down into thermal limits.

In addition to its high performance this twin shunt regulator circuit was selected because of the flexibility it offers in configuring XD0. Basic configurations of XD0 can be built installing only the series regulator and the filter caps on VAOSC buss. The dual shunt regulators can be left off entirely or added later as an upgrade.

Refer to the XD0 schematic sheet 6 titled "XD0 Power Regulators"

Here are the four three-terminal regulators used to power the analog output amps. Again the use of generous sized filter caps, long time constants on the v-set Rs and a load resistor to aid testing and bias them up. Not shown on the schematic is the PCB implementation. Using SMD V-set resistors and mounting adjust pin bypass caps on the bottom side of the PCB results in a very compact layout aiding both performance and packaging of the circuit.

Also shown on this sheet are power input connectors J7, J8, and J9. Again, flexibility is the watchword. Depending on how these are supplied and wired single or dual mono analog supplies can be used. One also has the option of using one or two DC supplies for VDD & VEE.

XD0 Clock, Control, & Reset

Refer to the XD0 schematic sheet 7 titled "XD0 Clock, Control, & Reset"

The Master Clock circuit is made up of OSC1 or OSC2. Note that the oscillator modules selected have 'inhibit' or shut down pins (pin 1 INH). Using these one of the two oscillators can be selected and the second shut down. By installing two different frequency oscillator modules optional upsampling rates can thus be featured. While this is a nice tweak to play with it is envisioned the more typical XD0 will only populate the OSC1 location. On the XD0 PCB the Master Clock is located on the bottom of the board right beneath the DAC. The SMD oscillator modules used allow this stacking getting the vital clock within fractions of an inch from the device it serves.

The Reset circuit uses U20 a Maxim MAX707 monitor chip to provide reliable power up and manual resets. The divider R58/59 and input/output on J12 accommodate a possible future battery charge monitor for those of you who want to try battery power for your XD0.

The Control And Status circuit is made up of J10, J11, RP3, RP4, and LED1-7. Using 0.1" center dual row connectors for J10 and J11 allows easy mounting of the devices on the XD0 PCB or using one of the many connectors available in this format remote mount then on a front panel. Note the presence of VDD on J10 pin 1 should a future front panel PCB require power.

XD0 Tubed Analog Stage

Refer to the XD0 schematic sheet 8 titled "XD0 Tubed Analog Stage"

This is an OPTIONAL alternative analog stage for XD0 using vacuum tubes. When this stage is used it replaces all the parts on sheet 4 "XD0 Analog Stage" which also means the four regulators on sheet 6 "XD0 Power Regulators" are not needed. The power supply and regulators for this tube stage is not shown. A prototype using a high voltage version of the Audio Crafters Guild SSPS with EL84 shunt regulation as been built and will be made public once XD0 is in production.

This tube stage is a differential follower published on "The Tube CAD Journal" site by John Broskie. Broskie's used 6DJ8 tubes, this has been adapted for and tested using the similar 6N1P. This circuit was chosen because it satisfied four major criteria needed for this application:

1. Differential inputs,

2. Low output impedance, i.e. good load drive,

3. Low or no gain,

4. Simplicity.

The Broskie Follower met all these criteria so a prototype was built for listening tests. Using X-DAC 3.24 as a stand-in for XD0 the results were outstanding through the Broskie Follower. For details of the Broskie Follower refer to the Tube CAD Journal June and October 1999 issues at www.tubecad.com. Also if you are at all interested in tube audio you MUST buy the Tube CAD software, its GREAT.

XD0 Beta Testing Program

The circuit described above has been laid out on a PCB (printed circuit board). Three of the PCB's four layers are completed. The fourth layer, the ground plane, awaits completion. I chose this point in the design process to make the XD0 design public as it represents the last chance for comment, changes, and corrections before casting the circuit in copper, fiberglass, silicon, and plastic. My hope is that from the DIY audio community there will emerge a core of XD0 beta testers who wish to both help with design chores and add input to the design. Two have already stepped forward, I would like to see three or four more of you take an active part. If you like what you see in the XD0 concept and design consider joining us.

While information on XD0 is free and open and comments from all are welcomed I decided to ask for a $50 deposit from XD0 beta testers. This will be held and applied towards the cost of your circuit board and parts kit or completed XD0. I am asking this for two reasons:

1. Four layer PCB startup costs are expensive. My preferred FAB house quotes $250 setup and production costs to get the first boards out. Experience says that could easily go to $400-$500 if we miss a few mistakes and run into layer &/or drill revisions. ACG will bear most of the PCB and parts stocking costs but a little help will be most welcome.

2. Money talks, bullshit walks. Pardon the vulgarity but if you have hung around audiophiles for awhile, and especially Internet audiophiles, you know that many are all talk and no action. If the vision for XD0 is to become a reality we have to stay focused. I need the XD0 beta testers invested both figuratively and literally. Now I love to talk audio gear as much as the next guy. All during the XD0 design process comments are welcome from one and all. However I do not have the luxury of spending every night answering e-mails from individuals who prefer discussing over doing and listening. You know the type. After exchanging 12 e-mails delving into the arcane details of audio design as preached in Stereophile while suggesting radical design changes he will leave declaring "I've decided to wait to see how the SACD/DVD-A format war settles out". While that is a valid decision PLEASE do not waste time on this project looking for validation of a wait and see attitude. XD0 is about actively pushing the boundaries of the state of the art in all digital audio formats.

The following tasks need to be completed before XD0 is released for PCB fabrication:

1. Complete power and ground system design. DONE

2. Peer review rev 2.1 schematics.

3. Peer review rev 2.1 PCB layout checking especially correct trace routing and parts footprints.

4. Update schematics incorporating any changes from steps 1 & 2. DONE

5. Update PCB layout adding ground plane and any changes found above. IN PROCESS

6. Re-check PCB layout for correct trace routing and parts footprints.

7. Generate Gerber files for four copper layers, drill files, top and bottom silk-screens, and solder masks.

8. Check Gerber files.

9. Release design to PCB fabrication shop.

The more eyes we get on the design during the above steps the better chance that we will have an error free PCB containing a solid design when completed. Working alone I got the X-DAC 3.24 design PCB layout done with zero errors routing wires to device pins. When I went to build them I discovered, to my considerable horror, that the CS43122 DAC IC footprint used the wrong width pad layout! Ahhhhh, it was one size to narrow. I was able to salvage the prototype by bending the IC's pins down. Soldered on the board the chip looked like a crab tip toeing across the beach. :-) Now of course I won't make THAT mistake again. What I am hoping is with your help we can catch the new mistake lurking on XD0 before it gets to a PCB.

Thank you for your attention and interest in ACG and XD0. If you are interested in becoming an XD0 beta tester let me know at the e-mail address below. Also keep checking the ACG web site as I will be posting XD0 updates.

Happy Listening
Norman Tracy
Audio Crafters Guild
5102 E 38 Place
Tulsa OK 74135 USA
918.627.5878 voice
ntracy@galstar.com e-mail
www.audiocraftersguild.com URL